Industry leading scan test tool
The Tessent TestKompress industryleading automatic test pattern generation (ATPG) tool delivers the highest quality scan test with the lowest manufacturing test cost. TestKompress uses a patented on-chip compression technique to create scan pattern sets that have dramatically less test data volume, which reduces test time on the automatic test equipment. Support for advanced fault models includes cellaware faults to ensure maximum defect coverage. TestKompress supports a hierarchical test approach that is the most effective test approach for today’s large and ever-growing design sizes. TestKompress can also be combined with Tessent LogicBIST to implement a hybrid solution that maximizes test efficiency and supports in-system test for long term reliability.
Key Features:
- Extensive fault model support, including stuck-at, transition, cell- aware, N-detect, timing-aware, bridge, IDDQ, path-delay, and user-defined
- EDT technology reduces tester time and data volume
- Additional 2X-4X compression can be achieved using EDT Test Points generated by Tessent ScanPro
- Channel sharing to non-identical cores provides up to 2X additional compression
- Broadcasting scan data improves compression up to 2X for designs with identical cores
- Supports low pin count test strategies (as few as one scan channel)
- Supports hierarchical test and pattern re-use, reducing test generation time, memory footprint, and pattern count for large designs
- Support for a wide range of on-chip PLL/OCC implementations for at-speed test
- Direct diagnosis of compressed patterns. Diagnosis-driven yield analysis with Tessent Diagnosis and Tessent YieldInsight.
