AMD Vivado™ is the design software for AMD adaptive SoCs and FPGAs. It includes: Design Entry, Synthesis, Place and Route, Verification/Simulation tools. The advanced features in AMD Vivado Design Suite help hardware designers reduce compile times and design iterations, while more accurately estimating power for AMD adaptive SoCs and FPGAs.
Features
- Device Support – for all Xilinx devices
- Vivado IP Integrator
- Vivado Simulator
- Synthesis and Place and Route
- Dynamic Function eXchange
- Vitis High-Level Synthesis
- Vivado Logic Analyzer
- Vivado Serial I/O Analyzer
- Vivado Device Programmer
- Debug IP (ILA/VIO/IBERT)
Advantages
AMD Vivado™ Meeting Fmax Targets
Achieving your Fmax target in a high-speed design is one of the most challenging phases of the hardware design cycle. AMD Vivado™ brings unique features such as Report QoR Assessment (RQA), Report QoR Suggestions (RQS) and Intelligent Design Runs (IDR) – these features help you close timing. Using RQA, RQS and IDR will help converge on your performance goals in days instead of weeks resulting in huge productivity gains.
Enable Faster Design Iterations
Design iterations are common as developers add new features and debug their designs. In many cases these iterations are incremental changes are within a small portion of the design. The Vivado Design Suite offers two key technologies that significantly reduce design iteration times: Incremental compile and Abstract Shell.
Accurate Power Estimation
While designing Adaptive SoCs and FPGA, early and accurate power estimation is critical to driving crucial design decisions. Power Design Manager is a next generation power estimation tool engineered to provide accurate power estimation early in the design process for large and complex devices such as Versal and UltraScale+™ families. This tool was specifically designed to provide accurate power estimations for devices with multiple complex hard IP blocks.
