Accelerate SoC design with place-and-route technology
Aprisa digital implementation is an RTL2GDSII solution that offers complete synthesis and place-and-route functionality for top-level hierarchical designs and block-level implementation. It’s tapeout quality correlation with signoff tools, both for STA timing and DRC, reduces design closure and ensures optimal performance, power and area (PPA).
Designing at advanced process nodes requires a new place-and-route paradigm to manage the increasing complexity. Aprisa is a detail-route-centric physical design platform for the modern SoC.
Key Features:
- Uses a unique detailed-route-centric architecture with unified hierarchical runtime data model
- Includes patented technologies for superior timing, power and die size
- Certified by leading foundries and ready for designs at advanced process nodes down to 7 nm
- Is interoperable with popular digital design flows with support of standard input/output formats
- Includes highly signoff-correlated analysis engines.
- Easy GUI and scripting support
