A Complete IC Design Capture Environment
Tanner S-Edit is an easy-to-use design environment for schematic capture and design entry. It gives you the power you need to handle your most complex mixed-signal IC design capture. S-Edit is tightly integrated with Tanner T-Spice, Analog FastSPICE (AFS), or Eldo simulators, the Tanner L-Edit IC layout tool, and the Calibre LVS and PEX tools. S-Edit helps you meet the demands of today’s fast-paced market by optimizing your productivity and speeding your concepts to silicon.
Key Features:
- Handles your most complex, fullcustom IC designs
- Native on OpenAccess
- Integration with AFS, Eldo and T-Spice simulators, allowing waveform cross-probing and direct viewing of operating point simulation results in the schematic
- Simulation can also be set up, launched and monitored using the Solido Design Environment
- Inherited connections are supported
- Schematic Compare visually displays differences between any two schematic or symbol views
- Cross-probe between schematic, simulation results, layout and Calibre LVS report with net/device highlighting
- Netlist multiple-views per cell including: SPICE, schematic, Verilog, Verilog-A and Verilog-AMS
- Integrated with L-Edit Schematic Driven Layout (SDL) module to speed the layout and ECO process
- Configurable schematic Electrical Rule Checks (ERC)
- Multiple library support with integrated library navigator
- Hierarchy Editor to create and manage configuration views
- Advanced array and bus support
- Integration with third-party revision control tools
- Import and export multiple standard formats
