Industry leading ATPG solution
Advanced design techniques used in today’s SoCs present significant challenges to achieving high-quality silicon test. Tessent FastScan is the gold standard in automatic test pattern generation (ATPG), with support for a wide range of fault models, comprehensive design rule checks, extensive clocking support, and innovative algorithms for performance-oriented pattern compaction. Its ability to be applied to any type of design makes it the most versatile ATPG solution available. Tessent FastScan is part of the Tessent Shell platform, which offers extensive capabilities for automation, customization, testability analysis, and debug.
Key Features:
- Extensive fault model support, including stuck-at, transition, cellaware, N-detect, timing-aware, bridge, IDDQ, path-delay, and userdefined.
- On-chip PLL / OCC support ensures precise at-speed test.
- Support for any common scan implementation. Fully integrated with Tessent Scan / ScanPro.
- Multi-processor ATPG reduces runtime without impacting coverage or pattern count.
- Effective handling of false and multicycle paths.
- Comprehensive design rule checking and testability analysis.
- Powerful Tessent Shell scripting environment for automation, introspection, and integration.
